The invention relates to a method of manufacturing a semiconductor device with a semiconductor element which comprises a semiconductor zone which is situated below an electrode, adjoins a surface of a semiconductor body, and substantially does not extend laterally outside the electrode, in which method an electrode is formed on the surface of the semiconductor body, after which semiconductor material adjoining the surface and not covered by the electrode is removed by an etching treatment, whereby the position of the semiconductor zone below the electrode is defined.
During the etching treatment by which the position of the semiconductor zone relative to the electrode is defined, the electrode itself is used as a mask. The semiconductor zone is thus laterally bounded in a self-aligning manner during its formation in the semiconductor body.
U.S. Pat. No. 5,006,476 discloses a method of the kind mentioned in the opening paragraph whereby the electrode is formed in a doped layer of amorphous silicon deposited on the surface. The etching treatment which is subsequently carried out and by which the position of the semiconductor zone is defined is continued so long until the semiconductor material situated adjacent the electrode is removed through a depth which is substantially equal to that of the semiconductor zone to be formed. After the etching treatment has been carried out, the semiconductor body is heated to a temperature at which dopant diffuses from the electrode present at the surface into the semiconductor material. This treatment is continued until the semiconductor zone has reached the desired depth.
The known method forms not only the electrode in the layer of polycrystalline silicon, but also a pattern of conductors of which the electrode forms part. These conductors are provided with a top layer of a metal silicide so as to ensure that connections formed by the pattern of conductors have a comparatively low electrical resistance. This is achieved in that the conductors, after they have been formed, are provided with a layer of insulating material at their lateral faces, in that subsequently a metal layer is deposited over the entire assembly, and in that subsequently a heat treatment is carried out whereby the metal silicide is formed through reaction of the metal with the amorphous silicon. Since the metal layer does not react with the layer of insulating material on the lateral faces of the conductors, the latter are provided with metal silicide layers at their upper sides only. This takes place in a self-aligning manner.
This method of providing the conductors with well-conducting top layers is not only complicated, but also has the disadvantage that the top layer has a comparatively high electrical resistance. Silicides have an electrical resistance which is many times higher than that of metals usual in semiconductor technology, such as gold, copper, aluminium, and alloys of aluminium with copper and silicon.